`timescale 1ns / 1ps

// Top level module
module m3_core_die(
    input clk,
    input rst,
    output valid
);

wire [31:0] data_to_grp;
wire grp_valid;

smmu_pcie_wrap_down smmu_pcie_wrap_down_u(
    .clk(clk),
    .rst(rst),
    .data_out(data_to_grp)
);

m3_core_grp_dn m3_core_grp_dn_u(
    .clk(clk),
    .data_in(data_to_grp),
    .valid_out(grp_valid)
);

endmodule

// Intermediate module
module m3_core_grp_dn(
    input clk,
    input [31:0] data_in,
    output valid_out
);

wire crg_clk;
wire [31:0] internal_data;

top_crg_wrapper top_crg_wrapper_u(
    .sys_clk(clk),
    .crg_clk_out(crg_clk),
    .data(internal_data)
);

assign valid_out = |internal_data;

endmodule

// Leaf module
module top_crg_wrapper(
    input sys_clk,
    output crg_clk_out,
    output [31:0] data
);

assign crg_clk_out = sys_clk;
assign data = 32'hDEADBEEF;

endmodule

// Another module
module smmu_pcie_wrap_down(
    input clk,
    input rst,
    output [31:0] data_out
);

assign data_out = 32'h12345678;

endmodule
